1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a NAND-structured amorphous silicon based semiconductor read-only memory (ROM) device, of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells whose source/drain regions are formed from amorphous silicon and constructed based on a silicon-on-insulator (SOI) structure.
2. Description of Prior Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the binary code to be permanently stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
Most ROMs are identical in semiconductor structure except for the different binary code stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for data programming and then the semi-finished products are stocked in inventory awaiting customer orders. The customer then furnishes the data to the factory where the data are stored into the semi-finished ROMs by using the so-called mask-programming process. This procedure is now a standard method in the semiconductor industry for fabricating ROMs.
In most conventional ROMs, metal-oxide semiconductor field-effect transistors (MOSFET) are used as the memory cells for permanent storage of binary data. In the mask-programming process stage, an impurity material is doped into selected channel regions so as to provide the associated memory cells with different threshold voltage levels representing the storage of different values of the binary-coded data. Whether one MOSFET memory cell is set to store a binary digit of 0 or 1 depends on whether the associated channel region is doped with impurities or not. If one channel region is doped with impurities, the associated MOSFET memory cell is set to a low threshold voltage, effectively setting the MOSFET memory cell to a permanently-ON state representing the storage of a first binary digit, for example 0; otherwise, the MOSFET memory cell is set to a high threshold voltage, effectively setting the MOSFET memory cell to a permanently-OFF state representing the storage of a second binary digit, for example 1.
One conventional ROM device is shown in FIGS. 1A through 1C, in which FIG. 1A is a schematic top view of the ROM device; FIG. 1B is a cross-sectional view of the ROM device of FIG. 1 cut along the line IB--IB; and FIG. 1C is a cross-sectional view of the ROM device of FIG. 1 cut along the line IC--IC.
As shown, the conventional ROM device includes a semiconductor substrate, such as a P-type silicon substrate, on which a plurality of parallel-spaced bit lines 11 and a plurality of parallel-spaced word lines 13 crossing the bit lines 11 are formed. The word lines 13 are isolated from the underlying bit lines by an oxidation layer 12. This ROM device includes an array of MOSFET memory cells 14, each being associated with one segment of the word lines 13 between each neighboring pair of bit lines 11.
As shown in FIG. 1C, in the method for fabricating the conventional ROM device, the first step is to conduct an ion-implantation process so as to dope an N-type impurity material, such as arsenic (As), into selected regions of the substrate 10 to form a plurality of parallel-spaced diffusion regions serving as the bit lines 11. The interval region between each neighboring pair of the bit lines 11 serves as a channel region 16. Subsequently, a thermal oxidation process is performed on the wafer so as to form the oxidation layer 12 over the entire top surface of the wafer. Next, a conductive layer, such as a highly-doped polysilicon layer is formed over the wafer, and then selectively removed through a photolithographic and etching process. The remaining portions of the conductive layer serve as the word lines 13. This completes the fabrication of a semi-finished product of the ROM device awaiting for customer order.
In the mask-programming process, a mask layer 15 is first formed over the wafer. This mask layer 15 is predefined to form a plurality of contact windows according to the bit pattern of the binary-coded data that are to be programmed into the ROM device for permanent storage. These contact windows expose those channel regions that are associated with a selected group of the MOSFET memory cells of the ROM device that are to be set to a permanently-ON state. The covered MOSFET memory cells are to be set to a permanently-OFF state. Subsequently, an ion-implantation process is performed on the wafer so as to dope a P-type impurity material, such as boron (B), through the contact windows in the mask layer 15 into the exposed channel regions. This completes the so-called code implantation process.
In the finished product of the ROM device, the doped channel regions cause the associated MOSFET memory cells to be set to a low threshold voltage, effectively setting those MOSFET memory cells to a permanently-ON state representing the permanent storage of a first binary digit, for example 0. On the other hand, the undoped channel regions cause the associated MOSFET memory cells to be set to a high threshold voltage, effectively setting those MOSFET memory cells to a permanently-OFF state representing the permanent storage of a second binary digit, for example 1.
In the foregoing ROM device, since the source/drain regions are formed in the substrate by ion implantation, the isolation between the source/drain regions and the substrate is poor. Moreover, since a diode junction is used for the isolation of the source/drain regions from the substrate, the leakage current will be increased as the applied voltage is increased. Still further, since the magnitude of this leakage current is proportional to the contact area between the source/drain regions and the substrate, the operating voltage is limited to a small magnitude for prevention of a large leakage current.